Senior SOC and IP Design Engineer, Google Cloud
- תל אביב
- משרה קבועה
- משרה מלאה
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field, or equivalent practical experience.
- 5 years of experience with digital logic design principles, Register-Transfer Level (RTL) design concepts, and languages such as Verilog or System Verilog.
- Experience with logic synthesis techniques to optimize Register-Transfer Level (RTL) code, performance and power as well as low-power design techniques.
- Experience in logic design and debug with Design Verification (DV).
- Experience with a scripting language like Python or Perl.
- Experience with design sign off and quality tools (e.g., Lint, clock domain crossing (CDC), etc.).
- Knowledge of SOC architecture and assertion-based formal verification.
- Knowledge of high performance and low power design techniques.
- Knowledge in one of these areas: PCIe, UCIe, DDR, AXI, ARM processors family.
- Define the SoC/block level design document such as interface protocol, block diagram, transaction flow, pipeline, etc.
- Perform Register-Transfer Level (RTL) development (e.g., coding and debug in Verilog, System Verilog), function/performance simulation debug and Lint/Cyber Defense Center/Formal Verification/Unified Power Format checks.
- Participate in synthesis, timing/power closure, and Application-Specific Integrated Circuit (ASIC) silicon bring-up.
- Participate in test plan and coverage analysis of the block and SOC-level verification.
- Communicate and work with multi-disciplined and multi-site teams.