SoC Design for Test (DFT) Engineer
- תל אביב
- ₪ 16,000 per month
- הכשרה
- משרה מלאה
- Bachelor's degree in Electrical Engineering, a related field, or equivalent practical experience.
- 3 years of experience with Design For Test (DFT) methodologies, DFT verification, and industry-standard DFT tools.
- Experience with ASIC DFT synthesis, simulation, and verification flow.
- Experience in DFT specification, definition, architecture, and insertion.
- Master's degree in Electrical Engineering.
- Experience working with ATE engineers (e.g., silicon bring-up, patterns generation, debug, validation on automatic test equipment, debug of silicon issues).
- Experience in IP integration (e.g., memories, test controllers, Test Access Point (TAP), and Memory Built-In Self Test (MBIST)).
- Experience in SoC cycles, silicon bringup, and silicon debug activities.
- Experience in fault modeling.
- Develop DFT strategy and architecture (e.g., Memory Built-In Self Test (MBIST), Automatic Test Pattern Generation (ATPG), hierarchical DFT).
- Complete all Test Design Rule Checks (TDRC) and design changes to fix TDRC violations to achieve high-test quality.
- Insert DFT logic, boundary scan, scan chains, DFT Compression, Logic Built-In Self Test, Test Access Point (TAP) controller, clock control block, and other DFT IP blocks.
- Insert and hook up MBIST logic including test collar around memories, MBIST controllers, eFuse logic, and connect to core and TAP interfaces.
- Document DFT architecture, test sequences, and boot-up sequences associated with test pins.
- טכנאי/הנדסאי/מהנדס/ת חשמל/אלקטרוניקה/מכונות - התמחות בבקרה ...
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