Formal Verification Graduate Engineer - Temporary position (1 year)
- תל אביב
- ₪ 16,000 per month
- זמנית
- משרה מלאה
- Develop Formal Test benches and Properties - Write and maintain System Verilog Assertions to formally verify RTL designs using industry-standard formal tools.
- Collaborating with Design and Verification Teams
- Contribute to Verification Planning and Coverage
- Define formal verification plans, track progress, and contribute to achieving verification completeness.
- Bachelor's degree in electrical engineering.
- Proficiency in System Verilog is essential.
- A proactive, self-driven individual with problem-solving and complex analysis capabilities.
- Capable of delivering results in a dynamic, agile environment, both independently and organization-wide
- Practical experience with Jasper is beneficial; familiarity with SV-UVM, Python, and Tcl is advantageous.
- Experience in Formal Verification or Dynamic Verification
- פיתוח לוחות מהי...
- הנדסאי/ת או מהנדס/ת חשמל / מכונות
- לפחות 3 שנות ניסיון בתחום מערכות ניטור ובקרה...
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