
Senior STA Engineer, Sub-Chip
- יקנעם
- משרה קבועה
- משרה מלאה
- Perform advanced Static Timing Analysis (STA) for HSIO at chiplet and FC level.
- Running Prime Time, review and debug timing paths, understand constraints, sdc generation, timing ecos generation.
- Identify convergence risks and work closely with physical design, RTL and DFT teams, ensuring convergence throughout various project stages.
- Responsible for a full timing closer and quality approval from pre-layout STA model through signoff.
- B.SC./ M.SC. in Electrical Engineering.
- At least 4+ years of hands-on STA experience.
- Experience in Prime Time and signoff methodologies.
- Excellent leadership capabilities.
- Knowledge in physical design flows and methodologies (Synthesis, PNR, DFT designs).
- Trong background of Prime time tool.
- Great teammate.