SoC Design for Test Engineer, Google Cloud

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Note: By applying to this position you will have an opportunity to share your preferred working location from the following: Tel Aviv, Israel; Haifa, Israel.Minimum qualifications:

Bachelor's degree in Electrical Engineering, a related field, or equivalent practical experience.

Candidates will typically have 3 years of experience with Design For Test (DFT) methodologies, DFT verification, and industry-standard DFT tools.

Experience with ASIC DFT synthesis, simulation, and verification flow.
Experience using Electronic Design Automation (EDA) test tools (e.g., Spyglass, Tessent, etc.).

Preferred qualifications:

Master's degree in Electrical Engineering.
Experience in IP integration (e.g., memories, test controllers, Test Access Point (TAP), and Memory Built-In Self Test (MBIST)).
Experience in fault modeling.
Experience in SoC cycles, including silicon bringup and silicon debug activities.
Experience working with ATE engineers (e.g., silicon bring-up, patterns generation, debug, validation on automatic test equipment, debug of silicon issues).

About the jobOur computational challenges are so big, complex and unique we can't just purchase off-the-shelf hardware, we've got to make it ourselves. Your team designs and builds the hardware, software and networking technologies that power all of Google's services. As a Hardware Engineer, you design and build the systems that are the heart of the world's largest and most powerful computing infrastructure. You develop from the lowest levels of circuit design to large system design and see those systems all the way through to high volume manufacturing. Your work has the potential to shape the machinery that goes into our cutting-edge data centers affecting millions of Google users.As a SoC Design for Test (DFT) Engineer, you will be responsible for defining, implementing, and deploying advanced DFT methodologies for digital or mixed-signal chips. You will define silicon test strategies, DFT architecture, and create DFT specifications for next generation SoCs. You'll design, insert, and verify the DFT logic and prepare for post silicon and co-work/debug with test engineers. In addition, you will be responsible for reducing test cost, increasing production quality, and enhancing yield.Behind everything our users see online is the architecture built by the Technical Infrastructure team to keep it running. From developing and maintaining our data centers to building the next generation of Google platforms, we make Google's product portfolio possible. We're proud to be our engineers' engineers and love voiding warranties by taking things apart so we can rebuild them. We keep our networks up and running, ensuring our users have the best and fastest experience possible.Responsibilities

Develop DFT strategy and architecture (e.g., hierarchical DFT, Memory Built-In Self Test (MBIST), ATPG).
Complete all Test Design Rule Checks (TDRC) and Design changes to fix TDRC violations to achieve high-test quality.
Insert DFT logic, boundary scan, scan chains, DFT Compression, Logic BIST, TAP controller, Clock Control block, and other DFT IP blocks.
Insert and hook up MBIST logic including test collar around memories, MBIST controllers, eFuse logic, and connect to core and TAP interfaces.
Document DFT architecture, test sequences, and boot-up sequences associated with test pins.

Google is proud to be an equal opportunity workplace and is an affirmative action employer. We are committed to equal employment opportunity regardless of race, color, ancestry, religion, sex, national origin, sexual orientation, age, citizenship, marital status, disability, gender identity or Veteran status. We also consider qualified applicants regardless of criminal histories, consistent with legal requirements. See also and If you have a disability or special need that requires accommodation, please let us know by completing our .

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