
Senior ASIC Verification Engineer
- הרצליה
- משרה קבועה
- משרה מלאה
- Create a thorough verification plan out of IP specification and implement it to completeness.
- Build UVM-compliant IP verification environment from scratch.
- Debug to find root cause of issues.
- Full-chip verification from planning stage to tape-out, including gate-level testing.
- Testing using both System Verilog and C.
- Work in a diverse environment, collaborating with power engineers, communication experts and SW developers.
- B.Sc. in Electrical Engineering from a leading university.
- Over 5 years of experience in complex ASIC verification.
- Experience in building IP verification environment.
- Experience in UVM methodology.
- Good knowledge in Verilog.
- Experience in embedded C programming – advantage.
- Good communication and interpersonal skills.