Ready for an intellectual challenge that combines Mathematics and CS theory in the context of hardware development? Keep reading. In this role you will be responsible for developing mathematical proofs using model checking tools, to find RTL(Verilog) bugs or prove their absence Not in the Formal domain? No worries, we offer thorough training to learn the theory and practice directly from our team expertsDescriptionIn this role you will be responsible for developing mathematical proofs using model checking tools, to find RTL(Verilog) bugs or prove their absence . The position is relevant for both Herzliya/ Haifa siteMinimum Qualifications
Excellent graduates from leading universities
Highly motivated
Preferred Qualifications
Analytical thinking
Education & Experiencestudent for B.Sc. in Computer Science and Math or Computer Science and Physics only with 2 semester remaining studies
