
Senior Design Verification Engineer, Google Cloud
- חיפה
- משרה קבועה
- משרה מלאה
- Bachelor's degree in Electrical Engineering or equivalent practical experience.
- 8 years of experience with creating and using verification components and environments in standard verification methodology.
- Experience verifying digital logic at RTL level using SystemVerilog or Specman/E for Field Programmable Gate Arrays (FPGAs) or ASICs.
- Master's or PhD degree in Electrical Engineering, or a related technical field.
- Experience with verification techniques, and the full verification life-cycle.
- Experience with performance verification of ASICs and ASIC components.
- Experience with ASIC standard interfaces and memory system architecture.
- Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
- Create and enhance constrained-random verification environments using SystemVerilog and Universal Verification Methodology (UVM) or formally verify designs with SystemVerilog Assertions (SVA) and industry leading formal tools.
- Identify and write all types of coverage measures for corner-cases.
- Debug tests with design engineers to deliver functionally correct design blocks.
- Close coverage measures to identify verification holes and to show progress towards tape-out.