
Junior Design Verification Engineer, Networking, Google Cloud
- חיפה
- משרה קבועה
- משרה מלאה
- Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, a related field, or equivalent practical experience.
- 1 year of experience creating and using verification components and environments in standard verification methodology.
- Master’s degree in Electrical Engineering, Computer Science, or a related field.
- Experience with Universal Verification Methodology (UVM), SystemVerilog, or other scripting languages (e.g., Python, Perl, Shell, Bash, etc.).
- Experience with CPU implementation, assembly language or compute SOCs.
- Plan the verification of digital design blocks by fully understanding the design specification and interacting with design engineers to identify important verification scenarios.
- Create and enhance constrained-random verification environments using SystemVerilog or formally verify designs with SystemVerilog Assertions (SVA) and industry leading formal tools.
- Identify and write all types of coverage measures for stimulus and corner-cases.
- Debug tests with design engineers to deliver functionally correct design blocks.
- Apply close coverage measures to identify verification holes and to show progress towards tape-out.