Principal Formal Verification Engineer
- תל אביב
- משרה קבועה
- משרה מלאה
- Define and execute advanced formal verification strategies for complex digital blocks and systems.
- Lead formal activities across multiple projects, ensuring scalability, completeness, and convergence .
- Guide the development of formal testbenches, properties, assertions, and coverage models.
- Collaborate with architects, RTL designers, and DV teams to identify formal targets and maximize design verification efficiency.
- Provide technical leadership and mentoring to other formal engineers and contribute to the growth of formal expertise within the organization.
- Evaluate and deploy state-of-the-art formal tools, flows, and methodologies to continuously improve formal verification coverage and impact.
- BSc or MSc in Electrical/Computer Engineering, Computer Science, or Mathematics.
- 15+ years of hands-on experience in Formal Verification within the semiconductor industry.
- Proven track record of formal verification execution
- Deep understanding of formal concepts, abstraction techniques, property development, and convergence strategies.
- Strong analytical, debugging, and problem-solving skills.
- Excellent communication and collaboration skills.
- A true passion for formal verification, with a desire to innovate and elevate the practice within a mature and advanced formal verification environment.
- A visionary mindset, eager to push the boundaries of formal adoption and impact across architecture, design, and methodology.
- Strong desire to influence product development by using formal insights to drive architectural and design decisions.
- Proven ability to work collaboratively in a team-oriented culture while bringing thought leadership to the formal domain.