
Senior Verification Engineer
- פתח תקווה
- משרה קבועה
- משרה מלאה
- Block Level verification of complex Design modules
- Cluster/system level testing including
- Simulating system level scenarios
- Performance evaluation
- Software debug
- Writing verification environments from scratch
- Integrating block level environments into cluster/system environments
- Extensive knowledge in System Verilog UVM verification methodologies (or Specman eUVM)
- Experience in writing complex block level verification environments including
- Definition of testplans
- Environment architecture and coding
- Debug and coverage closure
- Experience in system level testing
- BS in Electrical Engineering or related + 8 years of experience, or MS + 6 years of experience, or Ph.D. + 3 years of experience
- Experience with verification of complex digital designs, including processors, interfaces, and DSP blocks
- Familiarity with formal verification techniques and tools
- Knowledge of hardware description languages such as Verilog
- Experience with emulation and/or FPGA prototyping
- Knowledge in scripting Languages such as Python